基于高速存储平台的高性能RS编译码器设计

Design of Highly Efficient RS Encoder and Decoder Based on High-speed Memory Platform

摘要:

目前，星载高速存储设备中采用商用RS编译码IP核来实现数据纠错功能，能够实现的编译码最高速率为800 Mbps，只能依靠多个IP核同时工作达到吉比特高速数据存取速率的要求。星载存储数据发生错误的主要原因是存储区单粒子翻转和存储介质本身特性产生的单比特数据错误。针对星载存储数据的误码特性，本文提出一种RS编译码改进算法，通过对编码算法中的剩余多项式及译码算法中的伴随多项式进行降次处理，减小编译码过程中运算的迭代次数及计算量，以及对编译码算法中的基本运算单元有限域乘法器采用子项复用技术，实现对传统RS编译码算法的改进。结果表明改进后的编译码器能达到最高数据速率为10.5 Gbps，编码器资源较单个商用IP核减少15%，译码器资源减少40%，能够满足后续高速存储平台的应用要求。

Abstract:

Commercial IP core is currently used in the development of high-speed memory device to achieve date error correction,the maximum achievable encoding and decoding speed is 800Mbps， which can only rely on multiple IP cores working simultaneously to meet the requirements of gigabit high-speed data access rate. In view of the bit error characteristics of spaceborne storage data, this paper proposes an improved RS decoding algorithm, which reduces the number of iterations and the amount of computation in the decoding process by downgrading the residual polynomial in the encoding algorithm and the syndrome polynomial in the decoding algorithm, and adopts the sub-term multiplexing technology for the finite field multiplier of the basic operation unit in the decoding algorithm. The implementation results indicate that the maximum speed the encoder and decoder can achieve 10.5 Gbps， while the encoder resources is reduced by 15% and decoder resources reduced by 40% compared to a single commercial IP core, which can meet the application needs of high-speed of memory platform.