高速1553B智能通用总线测试平台设计

Design of high speed 1553B intelligent universal bus test platform

摘要:

传统的1?Mbps 1553B由于总线带宽受限，在航天测量控制领域正逐步被4?Mbps高速1553B总线替代。一般的高速1553B总线测试仪不具备精准时序控制、动态消息插入和系统故障恢复的功能，难以模拟系统实际工况。因此，通过各模式下总线的初始化配置和数据收发控制，采用SDRAM动态读取和硬件定时触发技术，结合基于心跳和消息监测的冗余总线控制机制，设计了一种高速1553B智能通用总线测试平台。通过调整消息长度、消息内容和消息间隔，验证了总线测试平台BC-RT、RT-BC、RT-RT以及MT监视功能的正确性，满足了精准时序控制、动态消息插入和系统故障恢复的需求。本平台可用于半实物仿真、时序功能的验证和系统真实负载状态的测试。

Abstract:

The bandwidth of traditional 1 Mbps 1553B bus is limited, so it is gradually replaced by 4 Mbps high-speed 1553B bus in the field of aerospace measurement and control. While the general high-speed 1553B bus tester does not have the functions of precise timing control, dynamic message insertion and system fault recovery, so it is difficult to simulate the actual working condition of the system. Therefore, a high-speed 1553B intelligent universal bus test platform is designed by using the bus initialization configuration and data transmit-receive control in each mode, SDRAM dynamic reading and writing, hardware timing trigger technology, as well as the redundant bus control mechanism based on heartbeat and message monitoring. By adjusting message length, message content and message interval, the correctness of the bus test platform functions including BC-RT, RT-BC, RT-BC and MT monitoring is verified, which meets the requirements of precise timing control, dynamic message insertion and system fault recovery. The platform can be used for hardware in the loop simulation, timing function verification and real system load status test.