基于FPGA的并行可配置Keystone实时处理架构设计*

The configurable parallel architecture design for real-time Keystone transform processing based on FPGA

摘要:

针对雷达高速运动目标脉间存在距离单元走动而不利于长时间积累的问题，采用 Keystone 变换技术补偿距离单元走动是雷达提升高速运动目标检测和 ISAR 成像性能的一种有效方法。但 Keystone 变换计算复杂度高，在工程上实现实时处理极为困难。提出一种并行度可配置的 Keystone 实时处理架构，支持增加并行度来提升处理性能，实现资源与处理性能的互换。通过仿真和板上验证表明，Keystone 处理架构是有效的。使用 Keystone 实时处理架构实现高速运算目标的相参积累与理论结果相比，最大相对误差小于 10e-8；在并行度为 1 的情况下，平均单频点 2048 脉冲的 Keystone 处理需小于 25μs，满足 Keystone 实时处理要求。

Abstract:

Aimed at the problem that long-term coherent integration is troublesome for the range migration of high velocity moving targets, the Keystone transform is employed for compensating the range migration and is an efficient method for improving the performance of high velocity targets detection and ISAR imaging. However, the implementation of Keystone transform in real time is very difficult for the high calculation complexity. In this paper, a configurable parallel architecture for the real-time Keystone processing is proposed, which can achieve the resources and performance exchange, by increasing the parallel number to improving the performance. The result of simulation and verification on board show that our architecture for the Keystone processing is effective, comparing to the theoretical result, the maximal relative error of which is less than 10e-8, when used to accomplish the coherent integration of high velocity targets, and which need about 25μs to achieve single frequency Keystone transform with 2048 pulses in average, meeting the real-time processing requirement, when setting the parallel number is 1.